Liquid crystal displays (LCDs) have been widely applied in electronic products such as notebook computers, flat TVs or mobile telephones due to their advantages of low radiation, small volume and low energy consumption.
A liquid crystal display generally has a structure as shown in FIG. 1. The liquid crystal display comprises a display panel 10 and a driving unit, which comprises a scan driver 210, a timing controller 220 and a data driver 230. The timing controller 220 outputs a vertical synchronizing signal STV and an enable signal OE to the scan driver 210, and a shift register 211 in the scan driver 210 shifts the received vertical synchronizing signal STV step by step to output a plurality of scan signals. A level shifter 212 receives scan signals and determines whether or not to output scan signals to the display panel 10 according to the enable signal OE. Referring to the waveform diagram of the enable signal OE and the gate row driving signal Gate in FIG. 2, when the OE signal is of low level, the Gate signals (G1, G2, G3, . . . ) are of low level; and when the OE signal is of high level, the Gate signals (G1, G2, G3, . . . ) are of high level. Coordinating the time sequence in which the scan driver 210 outputs scan signals, the timing controller 220 also outputs a horizontal synchronizing signal STH, a digital display data DD and a latch signal LP to the data driver 230, in which the horizontal synchronizing signal STH latches the digital display data DD in a corresponding channel in the latch 231, then determines whether or not to output the digital display data DD according to the latch signal LP, the digital display data DD is converted into display signals (D1, D2, . . . , Dm) by a digital to analog (D/A) converter 232 and input into the display panel 10 for image displaying.
In order to enhance the dynamic performance of a display panel 10, a polarity inversion technology is commonly used to drive the display panel 10. As shown in FIG. 2, during the enable period of the scan signal G1, the display signal D1 is of negative polarity with respect to the common voltage Vcom; during the enable period of the scan signal G2, the display signal D1 is of positive polarity with respect to the common voltage Vcom; and during the enable period of the scan signal G3, the display signal D1 is of negative polarity again with respect to the common voltage Vcom, and so forth. As such, the display signal D1 changes between the positive and negative polarities, and therefore the data driver 230 needs to consume much power. In order to reduce the oscillation amplitude of a signal output by the data driver 230 to save power consumption, a charge sharing technology may be applied.
A charge sharing technology is to provide a switch SW between two channels, as shown in FIG. 3. A first data channel 30 (outputting display signal D1) and a second data channel 31 (outputting display signal D2) will be described herein as an example. Prior to the transition between positive and negative polarities of the display signal of the data channel, the first and second data channel 30 and 31 are shorted by turning on the control switch SW. As such, electrical charges on the first data channel 30 and the second data channel 31 may be equally distributed such that voltages on the first data channel 30 and the second data channel 31 rise or fall to about the common voltage Vcom beforehand (as shown in FIG. 2 by the display signal D1). Therefore, the data driver 230 only needs to discharge voltages on data channels to a negative polarity voltage around the common voltage Vcom or charge them to a positive polarity voltage such that it is possible to reduce the oscillation amplitude of the display signal output by the data driver 230, thereby saving much power consumption caused by polarity inversion.